This invention relates to a data processing device and a data order converting method, and particularly to a data processing device and a data order converting method which enable output, in a predetermined order, of pixels inputted in a line scan order.
In the case where, for example, digital image data is to be transmitted (communicated) via a satellite link, the Internet or any other communication network, and in the case where digital image data is to be recorded to a recording medium such as a digital VTR (video tape recorder) or DVD (digital versatile disc), shuffling or scrambling is often performed on the image data for the purpose of noise prevention, security on the network and protection of copyright and broadcasting right. Shuffling is carried out by rearranging pixels arranged in the line scan order constituting an image.
In motion detection in conformity to the MPEG (Moving Picture Experts Group), which is a standard for image coding/decoding, block matching is carried out between a block consisting of 8xc3x978 pixels of a current frame as a processing target and a block of pixels within a search range of a temporally preceding (past) frame or a temporally succeeding (future) frame as a reference frame for the current frame. In such case, the search range must be detected from the reference frame, which is one frame. In the case where the search range is detected from one frame, when the image is supplied in the line scan order and stored into a memory, a number of pixels equal to the number of lateral pixels of the search range must be taken out by reading a number of lines equal to the number of longitudinal pixels of the search range from the memory and then cutting the read lines in the vertical direction. Therefore, the search range is detected by converting a plurality of lines of the reference frame constituted by pixels arrayed in the horizontal order to an image constituted by pixels arrayed in the vertical order, that is by rearranging the pixels arranged in the line scan order constituting the plurality of lines of the reference frame.
Moreover, rotation of an image by 90 degrees can be carried out by converting an image constituted by pixels arrayed in the horizonal order to an image constituted by pixels arrayed in the vertical order. Therefore, it can be carried out by rearranging the pixels arranged in the line scan order constituting the image.
Such technique of rearranging pixels constituting an image is used for various types of image processing.
FIG. 1 shows the structure of an example of a conventional image rearrangement device for converting an image constituted by pixels arrayed in the horizontal order to an image constituted by pixels arrayed in the vertical order.
In FIG. 1, digital image data to be a processing target is supplied to a parallel/serial conversion circuit 301 as parallel data of every four pixels as a unit in the line scan order. The parallel/serial conversion circuit 301 converts the parallel data supplied thereto of every four pixels as a unit to serial data and sequentially supplies the serial data to line memories 302 to 305 each having a storage capacity for one line.
The line memory 302 stores pixels from the parallel/serial conversion circuit 301. The pixels stored in the line memory 302 are shifted rightward every time pixels are newly supplied from the parallel/serial conversion circuit 301. Specifically, in the case where one pixel is noted, when pixels of one line are supplied after the noted pixel is supplied to the line memory 302, the noted pixel is outputted from the line memory 302 and supplied to the subsequent line memory 303.
Also, in the line memory 303, similar to the line memory 302, the pixels supplied from the line memory 302 are delayed by one line and supplied to the subsequent line memory 304. Similarly, the pixel data is delayed by one line in the line memories 304 and 305, respectively.
Therefore, in the case where certain four consecutive lines are noted, the pixels of the same column of the four lines are outputted in parallel from the line memories 302 to 305. Thus, in the rearrangement device of FIG. 1, four lines of an image constituted by pixels arrayed in the horizonal (row or lateral) direction is converted to an image constituted by pixels arrayed in the vertical (column or longitudinal) direction.
In the conventional technique, as described above, in the case where pixels constituting an image are to be rearranged, a number of line memories corresponding to the number of lines on which pixels are to be rearranged are required. Since each of the line memories need to have a storage capacity for one line constituting the processing target image, line memories having a large storage capacity are required in the case where the processing target image is a highly fine image used for HDTV (high definition television) or the like.
Moreover, the line memory is generally made up of an SRAM (static random access memory). Since an SRAM has a chip size approximately 10 to 20 times that of a DRAM (dynamic RAM) of the same capacity, the use of SRAMs for line memories causes an increase in the chip size in realizing LSI (large scale integration) of the device.
Meanwhile, as a technique for rearranging pixels constituting an image, other than the technique of rearranging pixels using line memories as buffers as shown in FIG. 1, there is a technique of preparing a frame memory for storing an image and then scrambling or shuffling either a write address used for writing the image to the frame memory or a read address used for reading the image stored in the frame memory. As a method for scrambling the write address or read address, a memory for address conversion having a scrambled address stored therein is prepared and the write address or read address is supplied to the memory for address conversion, thereby using the address outputted from the memory for address conversion as the scrambled address.
FIG. 2 shows the structure of an example of a conventional shuffling memory device for shuffling image data by scrambling a write address or read address.
The shuffling memory device is supplied with 8-bit image data, a write pulse, a read pulse and a write enable signal WE, which are shuffling targets. The image data is supplied to an I/O (input/output) selector 201. The write pulse is supplied to a write address counter 202. The read pulse is supplied to a read address counter 203. The write enable signal WE is supplied to the I/O selector 201, a selector 205 and a RAM (random access memory) 206.
In this shuffling memory device, the image data supplied to the I/O selector 201 is written to the RAM 206. After that, in reading the image data from the RAM 206, the read address is controlled. Thus, shuffling of the image is performed.
Specifically, at the time of writing the image data, the write enable signal WE is set at H-level indicating writing, of H (high)-level and L (low)-level, and is supplied to the I/O selector 201, selector 205 and RAM 206. On receiving the write enable signal WE of H-level, the I/O selector 201 selects image data to be a shuffling target and supplies the selected image data to an input/output terminal (I/O) of the RAM 206.
When the write enable signal WE is set at H-level, the write pulse starts to be supplied to the write address counter 202. In accordance with the write pulse, the write address counter 202 makes increment on the 8-bit count value by one. The 8-bit count value is outputted as a write address to the selector 205.
When receiving the write enable signal WE of H-level, the selector 205 selects the output from the write address counter 202 and supplies it to an address terminal (Address) of the RAM 206. Therefore, in this case, the write address outputted from the write address counter 202 is supplied to the RAM 206 via the selector 205.
In accordance with the write address supplied via the selector 205, the RAM 206 stores the image data supplied via the I/O selector 201. Thus, for example, in the case where the write address counter 202 generates a write address in accordance with the so-called line scan order, the RAM 206 stores the image data in the line scan order.
At the time of reading the image data thus stored in the RAM 206, the write enable signal WE is set at L-level indicating reading and is then sent to the I/O selector 201, selector 205 and RAM 206. On receiving the write enable signal WE of L-level, the I/O selector 201 selects the input/output terminal of the RAM 206.
When the write enable signal WE is set at L-level, the read pulse starts to be supplied to the read address counter 203. Similarly to the write address counter 202, the read address counter 203 makes increment on the 8-bit count value by one in accordance with the read pulse. The 8-bit count value is outputted as a read address to a RAM for address conversion 204.
The read address counter 203 outputs the read address which is the same as the write address outputted from the write address counter 202. Therefore, if this read address is supplied as it is to the RAM 206, the image data is read from the RAM 206 in the same order as in the case of writing to the RAM 206, that is, in the line scan order.
On receiving the read address from the read address counter 203, the address conversion RAM 204 outputs the 8-bit value stored at the address corresponding to the read address and thus converts the read address. Specifically, in the case where the read address which is the same as the write address is supplied from the read address counter 203, the address conversion RAM 204 converts the read address supplied from the read address counter 203 to a read address which is different from the write address. The read address after conversion outputted from the address conversion RAM 204 is supplied to the selector 205.
When receiving the write enable signal WE of L-level, the selector 205 selects the output from the address conversion RAM 204 and supplies the selected output to the address terminal of the RAM 206. Therefore, in this case, the read address after conversion outputted from the address conversion RAM 204 is supplied to the RAM 206 via the selector 205.
In accordance with the read address after conversion supplied via the selector 205, the RAM 206 reads the image data stored at the corresponding address. Since the read address after conversion is different from the write address, as described above, the image data is shuffled by reading the image data from the RAM 206 in accordance with the read address after conversion. This shuffled image data (hereinafter suitably referred to as shuffled data) is outputted to the I/O selector 201.
Since the I/O selector 201 selects the output of the RAM 206 as described above, the shuffled data read out from the RAM 206 is outputted via the I/O selector 201.
It should be noted that the address conversion RAM 204 can also be made up of a ROM (read-only memory) instead of a RAM.
In the case where the technique of preparing a frame memory for storing an image and then scrambling or shuffling either the write address used for writing the image to the frame memory or the read address used for reading the image stored in the frame memory is employed to rearrange the pixels constituting the image, and where the technique of preparing an address conversion memory having an scrambled address stored therein and then supplying the write address or read address to the address conversion memory so as to generate the scrambled address is employed as the method for scrambling the write address or read address, as described above, the time for accessing the address conversion memory is required in addition to the time for accessing the frame memory. Therefore, the processing is delayed.
Specifically, in the conventional shuffling memory device shown in FIG. 2, the address conversion RAM 204 for converting the read address to a read address which is different from the write address is necessary in addition to the RAM 206 as a buffer for temporarily storing image data. Therefore, the processing requires a longer time by the amount equal to the time for converting the read address in the address conversion RAM 204, that is, the time for accessing the address conversion RAM 204. Accordingly, the processing might result in breakdown in the case where an image is to be shuffled in real time.
As a method for reducing the time required for shuffling, a high-speed memory may be used for the RAM 206. For example, a synchronous DRAM (dynamic RAM) is known as a high-speed memory.
However, if a high-speed synchronous DRAM is used for reducing the time required for shuffling, reading/writing of data can only be carried out serially. Therefore, in the case where a synchronous DRAM is used in place of the RAM 206 of FIG. 2, it is necessary to shuffle the data to be serially written on the stage preceding the synchronous DRAM and then write the data to the synchronous DRAM. Accordingly, a buffer for temporarily storing the data is necessary on the stage preceding the synchronous DRAM. That is, while the RAM 206 in FIG. 2 is provided for shuffling the data, the use of the synchronous DRAM in place of the RAM 206 requires the buffer on the preceding stage, which is wasteful and therefore not preferred.
FIG. 3 shows an exemplary structure in the case where a DRAM chip is used for the shuffling memory device. In FIG. 3, a DRAM chip is shown in which data reading and writing are carried out at separate timings.
The DRAM chip shown in FIG. 3 is supplied with a row address and a column address as addresses for specifying a memory cell, a RAS (row address strobe) signal synchronized with the input timing of the row address, a CAS (column address strobe) signal synchronized with the input timing of the column address, voltages VDD and Vss used as a power source, and a write enable signal WE indicating which of reading and writing is to be carried out. In the example of FIG. 3, the write enable signal WE is set at H-level in carrying out writing.
The RAS signal is supplied to a buffer 1R. In synchronization with the RAS signal, the buffer 1R outputs a synchronizing signal for latching a part of the address supplied to the DRAM chip as the row address, to a row address latch circuit 2R. In addition, the buffer 1R generates an EQYE signal based on the RAS signal and supplies the EQYE signal to one input terminal of an AND gate 9. That is, the RAS signal has a nature of a so-called chip enable signal, and on the basis of the chip enable signal, the buffer 1R generates the EQYE signal which is at H (high)-level when the DRAM chip is inactive and which is at L (low)-level when the DRAM chip is active.
The CAS signal is supplies to a buffer 1C. In synchronization with the CAS signal, the buffer 1C outputs a synchronizing signal for latching a part of the address supplied to the DRAM chip as the column address, to a column address latch circuit 2C. In addition, the buffer 1C generates a Dout control signal based on the CAS signal and supplies the Dout control signal to an output buffer 11. That is, the CAS signal has a nature of a so-called output enable signal, and on the basis of the output enable signal, the buffer 1C generates the Dout control signal for controlling the latch of data in the output buffer 11.
The row address latch circuit 2R latches a part of the address supplied to the DRAM chip as the row address in synchronization with the synchronizing signal from the buffer 1R, and supplies the row address to a row decoder 3R. On completion of the latch of the row address, the row address latch circuit 2R supplies a latch completion signal LCH indicating the completion to the column address latch circuit 2C.
The column address latch circuit 2C latches a part of the address supplied to the DRAM chip as the column address in synchronization with the synchronizing signal from the buffer 1C and the latch completion signal LCH from the row address latch circuit 2R, and supplies the column address to a column decoder 3C and an ATD (address transit detector) circuit 8.
The row decoder 3R decodes the row address from the row address latch circuit 2R and controls a row driver 4R on the basis of the decoding result. The column decoder 3C decodes the column address from the column address latch circuit 2C and controls a column driver 4C on the basis of the decoding result.
Under the control of the row decoder 3R, the row driver 4R drives a word line WL arranged in the row direction in a memory cell array 5 and thus designates a memory cell (storage unit) of the target row for reading/writing data.
Under the control of the column decoder 3C, the column driver 4C controls a column switch 7i, thereby connecting a bit line BL arranged in the column direction in the memory cell array 5 to a data bus D and connecting a bit line !BL to a data bus xe2x80x2D via an SA (sense amplifier) 6i. Thus, data reading from/writing to the memory cell is made possible.
In the drawings such as FIG. 3, xe2x80x9cBLxe2x80x9d with an upper line ({overscore ( )}) represents an inversion signal of each xe2x80x9cBLxe2x80x9d without an upper line ({overscore ( )}). In this specification, however, xe2x80x9cBLxe2x80x9d with xe2x80x9c!xe2x80x9d added thereto, that is, xe2x80x9c!BLxe2x80x9d, is used as a symbol representing xe2x80x9cBLxe2x80x9d with an upper line ({overscore ( )}) in the respective drawings.
The memory cell array 5 is constituted by a plurality of memory cells arrayed in the row direction and in the column direction. Specifically, the memory cell array 5 is constituted by, for example, arranging N memory cells in the row direction and M memory cells in the column direction. The memory cell array 5 also has M word lines WL in the row direction and N (sets of) bit lines BL and !BL in the column direction. The word lines WL are connected to the row driver 4R. The bit lines BL are connected to the data bus D via the column switch 7i set in the conductive state by the column driver 4C. The bit lines !BL are connected to the data bus !D via the column switch 7i set in the conductive state by the column driver 4C.
The position of each memory cell in the row direction is specified by the row address, and the position in the column direction is specified by the column address. That is, memory cells corresponding to points of intersection between the word line WL driven by the row driver 4R and the bit lines BL and !BL connected to the data buses D and !D by the column driver 4C are used as targets of data reading/writing.
A sense amplifier group 6 includes SAs 61 to 6N of the same number as the number of memory cells (number of memory cell columns) arrayed in the row direction of the memory cell array 5. The SA 6i (i=1, 2, . . . , N) amplifies and latches the data read from the memory cell as the reading target, and outputs the data to the data buses D and !D via the column switch 7i set in the conductive state by the column driver 4C.
The number of column switches 7i (i=1, 2, . . . , N) is the same as the number of SAs 6i, and the ON/OFF-state of these column switches is controlled by the column driver 4C. Specifically, the ON/OFF-state of the column switch 7i is controlled by a driving signal outputted from the column driver 4C on the basis of the decoding result of the column address in the column decoder 3C. When the column switch 7i is in the ON-state, it electrically connects the bit line BL connected to the sense amplifier 6i to the data bus D, and electrically connects the bit line !BL connected to the sense amplifier 6i to the data bus !D. Thus, the memory cells on the bit lines BL and !BL are set in a state such that reading/writing of data is possible.
In the DRAM chip of FIG. 3, N sense amplifiers 61 to 6N and N column switches 71 to 7N are actually provided. However, to avoid complication of the drawing, only one SA 6i and one column switch 7i are shown in FIG. 3.
The ATD (address transient detector) circuit 8 generates an ATD signal which is at H-level during the transition (switching) of the column address and which is at L-level otherwise, on the basis of the output from the column address latch circuit 2C, and supplies the ATD signal to the other input terminal of the AND gate 9.
The AND gate 9 calculates AND of the EQYE signal from the buffer 1R and the ATD signal from the ATD circuit 8, and supplies a short signal CY for generating a short circuit of the data buses D and !D to the column driver 4C.
As described above, the EQYE signal is at H-level only when the DRAM chip is inactive, and the ATD signal is at H-level only at the time of transition of the column address. Therefore, the short signal CY is at H-level only when the DRAM chip is inactive and at the time of transition of the column address. Otherwise, the short signal CY is at L-level otherwise. The column driver 4C generates a short circuit of the data buses D and !D when the short signal CY is at H-level, thereby erasing the data on the data buses D and !D. By doing so, it is possible to realize high-speed data reading/writing with respect to the memory cell array 5.
A main amplifier (MA) 10 is connected to the data buses D and !D. It amplifies data which is read from the memory cell array 5 and outputted on the data buses D and !D, and supplies the amplified data to the output buffer 11. The output buffer 11 latches the parallel data from the MA 10 in accordance with the Dout control signal from the buffer 1C, and outputs the latched data as serial data from an output terminal Dout.
An input buffer 12 is connected to an input terminal Din. It latches serial data as a writing target, inputted from the input terminal Din, and supplies the latched data as parallel data to a recording amplifier 13. The recording amplifier 13 amplifies the data from the input buffer 12 and outputs the amplified data onto the data buses D and !D.
The operation of the DRAM chip shown in FIG. 3 is as follows.
An address for specifying a memory cell for reading/writing data, a RAS signal and a CAS signal are entered to the DRAM chip shown in FIG. 3. The address is supplied to the row address latch circuit 2R and the column address latch circuit 2C. The RAS signal is supplied to the buffer 1R and the CAS signal is supplied to the buffer 1C.
The buffer 1R generates a synchronizing signal based on the RAS signal and supplies the synchronizing signal to the row address latch circuit 2R. The buffer 1C generates a synchronizing signal based on the CAS signal and supplies the synchronizing signal to the column address latch circuit 2C. The row address latch circuit 2R latches the address supplied thereto as a row address synchronously with the synchronizing signal from the buffer 1R, and outputs the latched address to the row decoder 3R. The column address latch circuit 2C latches the address supplied thereto as a column address synchronously with the synchronizing signal from the buffer 1C, and supplies the latched address to the column decoder 3C and the ATD circuit 8.
The column address supplied to the ATD circuit 8 is caused to be an ATD signal as described above and then passed through the AND gate 9, thereby providing a short signal CY. This short signal CY is provided as a signal which indicates the timing for forming a short circuit of the data buses D and !D to the column driver 4C, as described above.
At the time of data reading, data is read from the memory cell specified by the row address supplied from the row decoder 3R and the column address from the column decoder 3C in the above-described manner, and the data is outputted onto the data buses D and !D. However, the inversion data of the data read from the memory cell is outputted onto the data bus !D.
The data outputted on the data buses D and !D are amplified by the MA 10 and supplied to the output buffer 11. The output buffer 11 is also supplied with a Dout control signal generated by the buffer 1C, as described above. The output buffer 11 latches the data from the MA 10 in accordance with the Dout control signal and outputs the latched data from the output terminal Dout.
On the other hand, at the time of data writing, data as a writing target is entered to the input terminal Din and the writing target data is latched by the input buffer 12. The data latched by the input buffer 12 is amplified by the recording amplifier 13 and outputted onto the data buses D and !D. Then, the data on the data buses D and !D are written to the memory cell specified by the row address supplied from the row decoder 3R and the column address supplied from the column decoder 3C in the above-described manner.
In the DRAM chip shown in FIG. 3, since only one memory cell (or a memory cell group consisting of a plurality of memory cells on a certain word line) can be designated at a time by one set of the row address supplied from the row decoder 3R and the column address supplied from the column decoder 3C, as described above, data reading and writing can be carried out only at separate timing. That is, data reading and writing cannot be carried out at the same time.
In view of the foregoing status of the art, it is an object of the present invention to provide a data processing device and a data order converting method which enable high-speed rearrangement, that is, shuffling, of image data or the like while avoiding an increase in the size of the device as much as possible.
Disclosure of the Invention
A data processing device according to the present invention includes: a first decoding section for decoding a first address; a plurality of second decoding sections for decoding a second address; and a storage section having a plurality of storage units, one of which is specified by a pair consisting of a decoding result of the first decoding section and a decoding result of one of the plurality of second decoding sections. A first decoding result, which is a decoding result of one of the plurality of second decoding sections with respect to the second address, and a second decoding result, which is a decoding result of another one of the second decoding sections with respect to the second address, are different from each other.
At least one of the plurality of second decoding sections has a changeable decoding result with respect to the second address.
At least one of the plurality of second decoding sections is a content-addressable memory.
The data processing device according to the present invention also has a write control section for writing data to a storage unit of the storage section specified in accordance with the first decoding result, and a read control section for reading data from a storage unit of the storage section specified in accordance with the second decoding result.
The data processing device according to the present invention further includes a first switching section for switching the order of the data of the first unit, and a second switching section for switching the order of the data of the second unit. The write control section writes the data outputted from the first switching section to the storage section on the basis of the first decoding result, and the read control section reads the data stored in the storage section on the basis of the second decoding result and supplies the data to the second switching section.
The first switching section switches the order of the data of the first unit by rotating the data of the first unit, and the second switching section switches the order of the second unit by rotating the data of the second unit.
The first unit and the second unit are equal to each other.
The first switching section and the second switching section have opposite rotating directions.
The data of the first unit is supplied to the first switching section as parallel data, and the data of the second unit is supplied from the second switching section as parallel data.
The data is image data.
The first address is a vertical address and the second address is a horizontal address.
The first decoding section, the second decoding section and the storage section are provided within one semiconductor chip.
The plurality of second decoding sections are operable at the same time.
Also, in the data processing device according to the present invention, each of the plurality of the second decoding sections includes a plurality of decoders, and the plurality of decoders output the decoding result when a preset address and the second address coincide with each other.
A data order converting method according to the present invention includes: a first change step of sequentially changing the order of a plurality of data supplied every first unit; a first decoding step of decoding a first address which is changed every time the order of the plurality of data of every first unit is changed; a write step of writing the data to a storage position in a storage section determined on the basis of a decoding result of the first address; a second decoding step of decoding a second address; a read step of reading the data every second unit from a storage position in the storage section determined on the basis of a decoding result of the second address; and a second change step of changing the order of the data of every second unit read from the storage section every time the second address is decoded.
The first change step includes switching of the order of the data of the first unit by rotating the data of the first unit, and the second change step includes switching of the data of the second unit by rotating the data of the second unit.
The first unit and the second unit are equal to each other.
The first change step and the second change step have opposite rotating directions.
Also, in the data order converting method according to the present invention, at the first change step, the data of the first unit is supplied as parallel data, and at the second change step, the data of the second unit is outputted as parallel data.
The data is image data.
The first address is a vertical address and the second address is a horizontal address.